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Qualcomm IC Package Design Integration Engineer in Hsinchu City, Taiwan


Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary

The ever-increasing requirement for data and processing bandwidth driven by the growth 5G networks, autonomous driving vehicles and carrier service scaling are creating technology demands which discrete component designs are struggling to address. Heterogeneous integration of chips and devices with high density interconnect module designs have the promise to address these technology challenges and create a new system design paradigm. We are looking for an experienced multi-chip packaging integration lead who has the passion to help lead this effort. The person should possess knowledge for wafer bump, assembly, substrate technology, material trends and flip-chip package designs and will be able to lead cross multiple disciplines to address the technology challenges. His/Her responsibilities include, but not limited to: Explore and recommend the packaging solutions and define POR for QCOM's multi-chip module designs; facilitate product package risk assessment, mitigation plans, and establishing best known processes methodology to ensure robust package quality, reliability, and manufacturing yield; coordinate technical development for new design attributes across partner teams from design to manufacturing (bump and assembly process and substrate technology); drive DFM/DFR/DFT, and TV design to identify the critical process window and material attributes.

Additional Requirements:

  • Hands-on experience with Cadence APD/SIP or Mentor Expedition/Xpedition

  • Good EE fundamentals and solid signal and power integrity fundamentals

  • Experience/knowledge in the packaging technology including substrate, bump and assembly process Experience in package design, design for manufacturing review

  • Familiar with layout review tools such as Valor or Calibre

  • Experience preferred in schematic capture, layout and design using Cadence Allegro Schematic Design Entry (Concept HDL) design tools is a plus

  • Excellent communication and organizational skills


  • Frequently transports between offices, buildings, and campuses up to ½ mile.

  • Frequently transports and installs equipment up to 5 lbs.

  • Performs required tasks at various heights (e.g., standing or sitting).

  • Monitors and utilizes computers and test equipment for more than 6 hours a day.

  • Continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

Minimum Qualifications


Bachelors - Engineering, Bachelors - Science

Work Experiences:

5+ years ASIC design, verification, or related work experience.



Preferred Qualifications


Bachelors - Computer Engineering, Bachelors - Computer Science, Bachelors - Electrical Engineering

Work Experiences:

1+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above). ,2+ years experience with design verification methods. ,2+ years experience with scripting tools and programming languages. ,2+ years experience with architecture and design tools. ,8+ years ASIC design, verification, or related work experience.



ASIC Verification, Matlab C, Multicore System-On-Chip (SoC), Perl Programming, Simulation Software

Applicants : If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email to accommodationsupport

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If you would like more information about this role, please contact Qualcomm Careers ( .

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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